1. Field of the Invention
This invention relates to the structure and fabrication of electrical feedthroughs, and more particularly to a conductive via structure and fabrication method used to electrically connect the front face of a solar cell to its back face in a coplanar contact configuration.
2. Description of the Related Art
There are a number of applications in which an electrical connection needs to be made through a substrate so that circuitry on one face of the substrate can be electrically contacted by making physical contact to the opposite substrate face. For example, multilayer or 3-D integrated circuit chips can be stacked on top of each other, with circuitry on the upper face of each chip interconnected with circuitry on the other chips by means of conductive vias through the chips. Multilayer photonic devices also make use of electrical feedthroughs through the individual layers. Another example is a solar (photovoltaic) cell in which a voltage differential is developed across the opposite faces of the cell, but it is desired to electrically contact both faces with coplanar contacts made to the back face alone. While the present invention is primarily concerned with a coplanar contact solar cell, it is generally applicable to electrical feedthroughs for other applications also.
A conventional solar cell 2 is illustrated in FIGS. 1 and 2. The cell is formed from a semiconductor material such as silicon, with its front face 4 oriented for illumination by the sun. An abrupt discontinuity in the conductivity type of the cell material is created through the addition of dopants. In the example shown in FIG. 2, the portion of the semiconductor above junction 6 is doped n-type, while the portion below junction 6 is doped p-type. The semiconductor will absorb characteristic photon energies from the visible light spectrum to produce photo-generated electrical carriers, and thus induce a voltage differential between the front face 4 and rear face 8 of the cell.
An electrical connection is made to the front face of the cell by means of conductive leads 10 that extend across the front face and are connected together by a conductive strip 12 along one edge of the cell. This configuration allows sunlight to enter the cell through the areas that are not shaded by the front face conductors; typically about 95% of the front face is exposed. Contact to the rear face 8 is made by means of a metallic sheet 14 which may cover that face.
The voltage developed by the cell can be accessed by making separate electrical contacts to the terminal strip 12 and conductive sheet 14. However, in numerous applications it is desirable that both connections, be made to only one side of the cell. For example, in solar arrays for space use in which thousands of cells must be interconnected, the increased complexity of building a coplanar contact cell (both contacts on only one side of tile cell) is more than offset by the reduced assembly cost of the coplanar configuration.
To establish an electrical contact to the front face terminal strip 12 from the rear of the cell, an extension of the terminal strip 12 may be wrapped around the edge of the cell and brought to an area on the back face that is insulated from the conductive sheet 14 and the semiconductor material on that side of the cell. This type of connection, which is referred to as a "wraparound" contact, is disclosed in numerous publications such as M. Gillanders et al., "High Efficiency Wraparound Contact Scalar Cells" 14th IEEE Photovoltaic Specialists Conference, 1980, pages 146-150; K. Matthei, "Optimization of Large Area Solar Cells for Low Cost Space Application", 15th IEEE Photovoltaic Specialists Conference, 1981, pages 228-232; D. Michaels et al., "Large Area, Low Cost Space Solar Cells With Optional Wraparound Contacts", 15th IEEE Photovoltaic Specialists Conference, 1981, pages 225-227; F. Ho et al., "Thin Foil Silicon Solar Cells With Coplanar Back Contacts", 15th IEEE Photovoltaic Specialists Conference, 1981, pages 102-106; and B. T. Cavicchi et al., "Large Area Wraparound Cell Development", 17th IEEE Photovoltaic Specialists Conference, 1984, pages 128-133.
To avoid having to extend a conductive strip around the edge of the cell, a "wrapthrough" connection has been developed recently that makes the connection directly through the cell body. This type of feedthrough arrangement is illustrated in FIG. 3, which shows a portion of the front face for a solar cell that has a radial and concentric circular network of conductor lines 16, rather than the rectangular grid lines 10 of FIGS. 1 and 2. The conductive lines 16 radiate outward from a terminal ring 18 to which they are all electrically connected. An opening or "via" 20 is centrally located within terminal ring 18, and extends down through the cell to the back face. The conductive material of terminal ring 18 extends through via 20 and coats its interior walls to establish an electrical connection between the front face conductor lines 16 and the back face of the cell. A similar via can be provided between the terminal strip 12 and the back face of the cell shown in FIGS. 1 and 2. Such "wrapthrough" vias are disclosed in several articles, such as D. Lillington et al., "Development of 8 cm.times.8 cm Silicon Gridded Back Solar Cell for Space Station" 19th IEEE Photovoltaic Specialists Conference, 1987, pages 489-493; D. Lillington et al., "Optimization of Silicon 8 cm.times.8 cm Wrapthrough Space Station Cells for `On Orbit` Operation" Proceedings of the 20th PVSC, 1988, pages 934-939; and A. Mason et al., "Development of 2.7 mil BSF and BSFR Silicon Wrapthrough Solar Cells" 21st IEEE Photovoltaic Specialists Conference, 1990, pages 1378-1382.
An example of a prior "wrapthrough" via is shown in FIG. 4. An active solar cell region 22 is formed on a doped semiconductor substrate 24 that electrically functions as a conductor to bring the voltage developed on the underside of the active region to the cell's back face 26. A via opening 28 is established through the substrate, normally by laser scribing. A dielectric layer 30, typically SiO.sub.2, is deposited over the via walls and the adjacent front and back surfaces of the cell by low pressure chemical vapor deposition. A conductive metallic layer 32 is then deposited over the SiO.sub.2 layer 30, and extends beyond the dielectric on the front face of the cell to establish electrical contact with that portion of the active region. The conductive layer 32 is insulated from the substrate on its back face, but is exposed at that location so that it may be contacted coplanar with back face contact (not shown).
It is important that the exposed substrate surface which contacts the SiO.sub.2 coating in the via opening be quite smooth, as illustrated on the left hand side of the via 28. If the substrate surface is rough it may not be completely covered by the SiO.sub.2 layer. In this event the conductive metal 32 can come near or into direct contact with the substrate, resulting in a significant power loss and perhaps even short-circuiting the device entirely.
A problem with laser scribing via openings through semiconductors such as silicon and germanium is that the scribing operation produces an opening whose surface is quite rough. An aggressive etch is then typically employed to smooth the walls of the opening. Omitting the etch can result in the formation of pinholes or cracks in the SiO.sub.2 layer, resulting in the shunting of current into the substrate.
Solar cells have recently been developed with GaAs active regions on a Ge substrate. While these materials offer a higher conversion efficiency than silicon, GaAs is attacked by the strong etchants used to smooth the via walls, and must be isolated from the etchant by a protective mask. Unfortunately, it is difficult to fully mask the GaAs active region, and damage often results from the etching process. In theory this problem can be overcome by reversing the fabrication process, and forming the via through the Ge substrate before the GaAs active region is grown. But the process of forming the via often results in damage to the upper Ge surface so that a good epitaxial growth of GaAs upon the substrate surface cannot be achieved.
The degree to which cell performance is degraded by this type of limited shorting, shown on the right hand side of FIG. 4, is a function of the shunt resistance value, the operating voltage and the cell area. Based upon modeled results for GaAs/Ge cells, minimum shunt resistances of 400 ohms and 6,000 ohms are required to hold losses to less than 0.5% for cells with areas of 16 cm.sup.2 and 1 cm.sup.2, respectively. The conventional via structure described above is not capable of reliably meeting this requirement. Furthermore, dielectrics such as SiO.sub.2 that are deposited by low pressure chemical vapor deposition have poor adhesion to Ge.